The array tester described in U.S. Pat. No. 5,179,345 provides a means for comprehensively testing every cell in a TFT/LCD array using only the array's edge connections. The basic test performed by the array tester is to write charge onto a cell (by properly biasing the gate and data lines), store charge on the cell by biasing the gate off, read the remaining charge off of the cell by connecting a charge integrating circuit to the data line and biasing the gate line on, and then measure the charge that has been transferred to the charge integrating circuit to determine the final value of charge.
Electrically testing the charge arrays inherent to TFT/LC displays at any stage prior to the attachment of line drivers requires contacting a large number of pads (typically in the thousands). Contamination (such as residual photoresist, oxide films, etc.) and the substrate non-planarity can interfere with good electrical connection between the tester probes and the array pads. To insure validity of the many tests that write charge to, and read charge from, selected pixels, it is necessary to determine whether the tester probes are actually making contact to the array pads.
There are various mechanical ways to assure electrical contact to the pads. However, these require at least one of mechanical motion between the pads and the probes, the use of additional probes to determine the integrity of the electrical contact, or mechanical abrasion of the pads or gate lines. These procedures are expensive, time consuming and may themselves introduce possible sources of failure for the array under test. Thus, it is highly desirable that various electrical integrity checks can be made using only the probes normally required to contact the pads, and that these probes be used in the normal manner described in the above mentioned patent.